Modern electronic design automation (EDA) tools are devised to communicate design intent and the circuit behavior between a circuit designer and other technical personnel such as design team member. With the number of transistors in an integrated circuit (IC) doubling approximately every two years according to the Moore's law, contemporary electronic designs have become increasingly bigger and more complex over time. These contemporary electronic designs continue to face increasing size and complexity challenges as well as the employment of multiple asynchronous clock domains for different input/output (I/O) interfaces.
An electronic design having clock domain crossing violations is a circuit design that has one clock asynchronous to or has a variable phase relation with another clock. A clock domain crossing (CDC) signal may thus include a signal latched by a flip-flop (FF) in one clock domain and sampled in another asynchronous clock domain. Transferring signals between asynchronous clock domains may lead to setup or timing violations that may further cause signals to become meta-stable. Conventional approaches often address and verify such CDC errors late in the design cycles or even in the post-silicon verification.
The identification and fixes of CDC errors thus impose prohibitively high costs. In addition, these conventional approaches involve multiple techniques to identify CDC violations and CDC structures causing these CDC violations. These techniques require identifying the hardware description of an electronic design, elaborating and analyzing the representation of the electronic design (e.g., a full system on chip also known as SoC) in its entirety to generate a netlist model, and performing various analyses to identify possible CDC issues in the netlist model. Nonetheless, the sheer size of the electronic design not only requires a powerful computing system to manipulate the electronic design in its entirety but also crumbles the performance of such a computing system to a point that many modern computing systems simply cannot even handle the elaboration part, not to mention the subsequent analyses.
Therefore, there exists a need for a method, system, and computer program product for verifying an electronic design using hierarchical clock domain crossing verification techniques.